The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, more specifically a semiconductor device including capacitors and a method for fabricating the semiconductor device.
A DRAM (Dynamic Random Access Memory) comprises memory cells each including one transfer transistor and one capacitor and may only have a small area, and is a semiconductor memory suitable for mass storage. With recent increased information processing amounts of electronic equipments, etc. DRAMs used in the electronic equipments, etc. are required to be further micronized and have larger capacities.
A conventional method for fabricating a DRAM will be explained with reference to FIGS. 19A to 23B. In FIGS. 19A to 23B, the drawings shown on the left side are sectional views of the DRAM along a bit line of the DRAM, and those on the right side are sectional views along a word line of the DRAM.
As shown in FIG. 19A, first, a device isolation film 112 is formed on a silicon substrate 110 by LOCOS (LOCal Oxidation of Silicon).
Then, a gate oxide film (not shown) is formed on the surface of the silicon substrate 110.
Next, a polysilicon film 114, a tungsten silicide film 116, a silicon oxide film 118, a silicon nitride film 120 and a silicon nitride oxide film 122 are formed sequentially on the entire surface by CVD (Chemical Vapor Deposition) to form a laminated film 123 of these films is formed (see FIG. 19B).
Then, the laminated film 123 is patterned as required to form a gate electrode 124 of a polycide structure of the polysilicon film 114 and the tungsten silicide film 116. The gate electrode 124 functions as word lines which also function as gate electrodes of other transfer transistors which are extended vertically to the sheet of the drawing on the left side of FIG. 19C.
Next, with the laminated film 123 as a mask dopant ions are implanted into the silicon substrate 110 to form a source/drain diffused layer 126a, 126b by self-alignment with the laminated film 123 (see FIG. 19C).
Then, a silicon nitride film is formed on the entire surface and is anisotropically etched to expose the surfaces of the silicon substrate 110, the device isolation film 112 and the laminated film 123 to form a sidewall insulating film 128 on the sidewalls of the laminated film 123.
Then, a stopper film 130 of a silicon nitride film is formed on the entire surface.
Next, an inter-layer insulating film 132 of an about 0.5 .mu.m-thickness BPSG (Boro-Phospho-Silicate Glass) film is formed by CVD. The surface of the inter-layer insulating film 132 is planarized by reflow and CMP (Chemical Mechanical Polishing) (see FIG. 19D).
Then, a contact hole 134 for exposing the source/drain diffused layer 126b is formed in the sidewall insulating film 128 by self-alignment (see FIG. 20A).
Next, a conductor plug 136a is formed in the contact hole 134 (see FIG. 20B).
Then, an about 0.1 .mu.m-thickness silicon oxide film 138 is formed on the entire surface by CVD.
Then, a contact hole 140 for exposing the source-drain diffused layer 126a is formed on the sidewall insulating film 128 by self-alignment (see FIG. 21A).
Next, a polysilicon film 142, a tungsten silicide film 144, a silicon oxide film 146, a silicon nitride film 148 and a silicon nitride oxide film 150 are sequentially formed on the entire surface by CVD to form a laminated film 152 of these films. Then, the laminated film 152 is patterned as required to form a bit line 154 of a polycide structure of the polysilicon film 142 and the tungsten silicide film 144 (see FIG. 21B).
Then, a silicon nitride film is formed on the entire surface and is anisotropically etched until the surfaces of the silicon oxide film 138 and the laminated film 152 are exposed to form a sidewall insulating film 156 on the sidewalls of the laminated film 152. The sidewall insulating film 156 is for formation of a SAC (Self aligned Contact) so as to secure a large disalignment margin of micronized contact.
Next, an inter-layer insulating film 160 is formed on the entire surface. Then, the surface of the inter-layer insulating film 160 is planarized by CMP. Next, a silicon nitride film 161 is formed on the inter-layer insulating film 160 by CVD (see FIG. 21C).
Subsequently, a contact hole 162 for exposing the upper surface of the conductor plug 136a is formed. Then, a conductor plug 136b is formed in the contact hole 162 (see FIG. 22A).
Next, an about 1.7 .mu.m-thickness BPSG film 164 is formed on the entire surface by CVD. An opening 166 for exposing the upper surface of the conductor plug 136b is formed in the BPSG film 164. The opening 166 is for formation of a storage electrode 168 of a capacitor in a later step (see FIG. 23A). At this time the silicon nitride film 161 functions as etching stopper (see FIG. 22B).
Then an about 0.05 .mu.m-thickness polysilicon film is formed on the entire surface by CVD. Next, a resist is applied to the entire surface to form a resist film 170. Then, the polysilicon film and the resist film 170 are polished by CMP until the surface of the BPSG film 164 is exposed. The storage electrode 168 is thus formed of the polysilicon film inside the opening 166.
Subsequently, the BPSG film 164 is removed by HF-based wet etching. At this time the silicon nitride film 161 functions as an etching stopper (see FIG. 23A).
Then, the resist film 170 remaining on the inside of the storage electrode 168 is removed by ashing. Then, an about 8 nm-thickness tantalum oxide film 172 is formed on the entire surface by CVD. The tantalum oxide film 172 functions as a dielectric of a capacitor. Then, an 0.05 .mu.m-thickness titanium nitride film 174 and a 0.1 .mu.m-thickness polysiliicon film 176 are sequentially formed by CVD to form an opposed electrode 177 of a capacitor, which is formed of the titanium nitride film 174 and the polysilicon film 186 (see FIG. 23B).
Thus the conventional DRAM having the capacitor connected to the transfer transistor is fabricated.
However, in the conventional DRAM fabrication method, because close contact between the storage electrode 168 and the conductor plug 136b cannot be sufficiently secured, in removing the BPSG film 164 by HF-based wet etching, the storage electrode 168 is released from the conductor plug 136b, or the etchant intrudes at a vicinity of the upper surface of the conductor plug 136b to adversely etch regions which are not to be etched. Resultantly the DRAM has low yields.
To further micronize the DRAM, it is necessary to retain a capacity of the capacitor substantially equal to the conventional capacitor that the capacitor has an increased height, which leads to a larger step with respect to the peripheral circuit region. This results in a problem that it is difficult to form openings of the contact holes and the wiring.